Current driver system for a core memory

ABSTRACT

A system for supplying a current to a core memory stack having substantial inductance including a transformer having a selectively variable primary/secondary turns ratio. The variable turns ratio permits the current buildup time interval in the core state to be minimized while reducing the power required to drive the stack.

United States Patent Wells et al.

[451 Oct. 10, 1972 [72] Inventors: George H. Wells, Santa Ana; Perry B. Persons, lrvine, both of Calif.

[73] Assignee: Technology Marketing Incorporated,

Santa Ana, Calif.

[22] Filed: March 25, 1971 [21] Appl.No.: 128,030

[52] US. Cl. ..340/l74 TB, 340/174 AC 7/ 1967 Pechacek ..340/174 TB 3,482,1 18 12/1969 Mathamel ..307/270 OTHER PUBLICATIONS IBM Technical Disclosure Bulletin, Current Source Compensation by Hoffman vol. 10, No. 6, Nov. 1967, pp. 778; 340- 174 TB.

Primary Examiner'Stanley M. Urynowicz, Jr. Attorney-Fowler, Knobbe & Martens [57] ABSTRACT [51] lnt.Cl ..Gllc 5/02,Gllc 11/06 A S ystem for supplying a current to a core memory [58] Flew ofSearch"'34O/174 174 307/276 stack having substantial inductance including a transformer having a selectively variable primary/seconda- [56] References Cited ry turns ratio. The variable turns ratio permits the cur- UMTEDSTATES PATENTS rent buildup time interval in the core state to be minimized while reducing the power required to drive 3,239,681 3/1966 Bond ..340/174 TB thestack 3,603,938 9/1971 Cooper ..340/174 TB 3,332,074 7/1967 Arnold ..340/174 TB 14 Claims, 1 Drawing Figure 5 2 40% f6 2!) l7 fl 1;) 17 77M/IV6 (ONT/FOL E 57455 I I I] V i i [-10 This invention relates to improvements in magnetic core memories wherein an electrical conductor is threaded through a plurality of cores. Particular examples are coincident-current memories, linear-selection memories, and read-only core memories.

SUMMARY OF THE INVENTION Digital data processing systems require means for storing large quantities of digital data; Memories using a plurality of magneticcores or core stacks are commonly used for this purpose. Although such memory systems have been very extensively used for more than a decade and have several inherent advantages, factors which limit their functional utility include their electrical power requirements and their read-write cycle time.

A feature of the present invention is that it provides a simple, but elegant solution for the problem of reducing the power required to drive a core stack while minimizing the time interval required to build up the stack current drive to desired magnitude. As a result, core memories utilizing the' present invention can operate on a very short read-write cycle time while drawing minimal power.

Particular features of this invention are that it pro- 7 vides a balanced drive and is adapted for supplying core stacks characterized by a very substantial inductive load. Thus, a single system constructed in accordance with the invention can supply a current pulse through over 8,000 cores with a current buildup time of I00 nanoseconds while using less power than prior art devices.

In the preferred embodiment of the present invention, the core stack is connected to the secondary of the transformer and the primary of the transformer is initially energized through a current path having a minimal L/R time constant. As a result, a current of predetermined value is driven through the secondary winding and core stack within a very short time interval. The primary/secondary turns ratio is then changed while simultaneously reducing the current flow through the primary winding so that the power drain is reduced while maintaining the desired magnitude of current flow in the core stack.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the FIGURE, a transformer 10 having the dot convention shown includes series connected first primary winding 11 of N, turns and second primary winding 12 of N turns and a secondary winding 13 of N, turns. The secondary winding 13 provides a balanced output, i.e. neither output lead is grounded, which is very desirable for rejecting the common mode voltages generally present in a core stack. Advantageously, one end of the secondary 13 is connected to a pair of windings 14 and 15 of a core stack 16. Each of these windings 14, 15 are respectively threaded through a plurality of memory cores 17, as shown. A return current path to the other side of the secondary 13 is provided via diodes 18, 19. By way of particular example, cores 17 may represent a single bit plane of a coincident current memory and each of the windings 14, 15 represent the inhibit sense windings which are pulsed with a relatively short, e.g. 300 nanosecond, current pulse to inhibit the write current (on other windings not shown) in the bit plane when binary ZEROS are to be stored. While only a few cores 17 are shown for illustrative purposes, each of the windings 14, 15 may be threaded through literally thousands of cores. For example, in a core plane of 8,192 cores, each winding will be threaded through one-half of the total number of cores, e. g. 4,096 cores. As a result, the core stack and particularly the inhibit windings of a large core stack are characterized by a very substantial inductance.

The power for this current pulse is provided by a power supply voltage which supplies a voltage E between ground and the first primary winding 1 l. The current pulse is initiated by turning on transistor 20 which serves as a first switch. The collector of this transistor is connected to node 21 between the first and second primary windings 11, 12, its emitter is connected to ground, and its base to timing control stage 22. Accordingly, when transistor 20 is turned on by stage 22 a first current path is provided from voltage source E through the first primary winding 11 and transistor 20 to ground. This path has a minimal resistance and therefore a minimal L/R time constant. As a result, the current flow in the primary winding 1 1 and resulting current flow in secondary winding 13 build up to the desired magnitude in a minimal time interval.

After a predetemiined time interval, typically the relatively short interval required to buildup the current in the secondary winding to the desired magnitude, the timing control stage 22 turns transistor 20 off. Advantageously, transistor 25, serving as a second switch, has already been turned on by this same stage. The emitter of this transistor is grounded and its collector is connected through a series connected diode 26 and resistor 27 to the second primary winding 12. Accordingly, when transistor 25 is on and transistor 20 is off, a second current path is provided from voltage power supply E through the first and second primary windings 11, 12, resistor 27, diode 26 and transistor 25 to ground. This path, having a higher resistance provided by current limiting resistance 27, draws less current and therefore less power from the power supply than when current flows in the first current path provided by the first switch transistor 20.

Notwithstanding the reduced current and power drain when the first switch 20 is off and the second switch 25 is on, the magnitude of current flow through the secondary winding 13 is maintained at the desired value because of the increase in primary to secondary turns ratio. Thus, the relationship between the current and turns ratio are defined by the following equation:

I8=(NP/N8) n where 1,, is the current flowing through the primary, I is the current flowing through the secondary, N is the number of primary turns and N, is the number of secondary turns. N is the sum of the turns in the first and second primary windings or,

N, N N 3i If, for example, a current pulse of constant magnitude is desired, N,, N and N, may be made equal, and resistor 27 may be selected to reduce the primary current I, by one-half when the first switch is opened. Substituting these circuit ratios in equation (2), when switching transistor 20 is on 1/ p (4) If N, equals N,

When switching transistor is off and switching transistor is on, the secondary current is defined as follows, assuming theturns and current ratios given above:

Since it has been assumed that N N N I.= HQ

the same value derived in equation (5 The first switch 20 achieves the desired rapid current buildup in the core by minimizing the resistance in its circuit. Since this buildup requires a maximum power delivery from the power supply E the first switching transistor 20 is advantageously turned on for only the relatively short time interval required to build up the secondary current to the desired value. By way of specific example, for a current pulse width of 300 nanoseconds, the first switching transistor 20 is turned on for only 100 nanoseconds, a typical time required to buildupthe desiredcurrent magnitude in the secondary, after which the first transistor 20 is turned off and the second transistor 25 turned on for the 300 nanosecond pulse width; Accordingly, most of the power is delivered to the core stack while the system is drawing minimum power from-the power supply.

It will thus be seen that the system of the invention provides a primary/secondary turns ratio which is selectively varied over the pulse width of the output current pulse to provide the desired amplitude current flow through the memory core stack connected to secondary winding while limiting the overall power drain.

in the specific example above, a constant amplitude current is maintained over the pulse width. Similarly, the amplitude of the output current pulse may be increased or decreased over the pulse width by varying the number of turns on the two primary and secondary windings and/or by selecting a different value for the current limiting resistor 27.

Diode 26 is biased off when the first switching transistor is on; therefore, this diode prevents any current flow through the second current path regardless of the state of the second switching transistor 25. Thus, transistor 25 may be advantageously turned on at the same time that transistor 20 is turned on, since no current will pass through the second current path until the first switching transistor 20 is turned off resulting in forward bias on diode 26.

Also shown in the Figure is a resistive network 30 connected between respective ends of the stack windings 14, 15 and ground, and sense amplifier 31 connected between the sense windings 14, 15 for distinguishing between ONE and ZERO signals in the voltage outputs of the bit plane.

The remaining circuit elements are not used functionally during the production of the current pulse but instead decrease the magnitude and time duration of the voltage transients which occur when the timing control stage 22 terminates the current pulse by turning off the second switching transistor 25. The current then flowing through the large inductance of the stack causes a voltage to be induced in the secondary winding 13 which in turn induces a voltage in primary winding 11 and 12.

On the primary side of the circuit, resistor 35 and capacitor 36 are connected in parallel with the primary windings ll, 12, current limiting resistor 27 and diode 26. The capacitor 36 is charged when the transient voltage is induced on the primary windings 11, 12, thereby minimizing the transient voltage buildup at the collector of transistor 25. Resistor 35 and capacitor 36 together critically damp the voltage across the primary windings when the second switching transistor 25 is turned off.

On the secondary side of the circuit, one side of the secondary winding 13 is connected to a diode 40 clamped to a voltageE The other side of the secondary is connected through a resistor 41 to ground. These additional circuit components substantially limit the magnitude of the transient induced voltages induced when the second switching transistor 25 is turned off and also substantially decreases the time required forthe circuit to recover to its non-energized quiescent state.

What is claimed is:

1. A system for supplying a predetermined magnitude of current to a core memory, said system having a minimal current buildup time interval and a minimal power drain, comprising:

a transformer having first and second series connected primary windings and a secondary winding; means for connecting said secondary winding to said core memory; a voltage source; a first switch connected in series with said voltage source and said first primary winding to provide a first current path; a second switch connected in series with said voltage source and said first and second primary windings to provide a second current path; and means coupled to said first and second switches for i. closing said first switch for a sufficient interval to drive a current of predetermined value through said secondary winding to said core memory, and

ii. opening said first switch after said second switch has been-closed;

means coupled to said second current path to limit the current flow therethrough and thereby limit the power drain from said voltage source, the increase in primary/secondary turns ratio maintaining a desired magnitude of current flow through said secondary while decreasing the power drain from said voltage source.

2. The system described in claim 1 wherein said means coupled to said second current path to limit the current flow therethrough comprises a resistor.

3. The system described in claim 1 including means connected in said second current path for preventing the flow of current therethrough when said first switch is closed so that the closing of said second switch does not result in current flow through said second current path until after said first switch has been opened.

4. The system described in claim 3 wherein said means connected in said second current path is a diode.

5. The system described in claim 1 including a capacitor coupled to said primary windings, said capacitor being charged when the second switch is opened and the current flowing through the inductance of said core memory causes a voltage to be induced in the secondary winding which in turn induces a voltage in the primary winding.

6. The system described in claim 5 including a resistor connected in series with said capacitor so that the voltage across said primary winding is critically damped when the second switch is opened.

7. The system described in claim 1 wherein said first and second switches are transistors.

8. The system described in claim 1 wherein said secondary winding provides a balanced drive for the core memory wherein neither end of the secondary winding is grounded.

9. A system for supplying a current pulse to a core memory, said system having a minimal current buildup time interval and a minimal power drain comprising:

a transformer having a selectively variable primary/secondary turns ratio;

means for connecting the secondary of said transformer to said core memory; means for initially energizing the primary of said transformer through a current path having a minimal L/R time constant so that a current of predetermined value is driven through said secondary winding within a very short time interval; and

means for changing said primary/secondary turns ratio while simultaneously reducing the current flow through said primary so that the power drain is reduced while a desired magnitude of current flow is maintained through said secondary winding.

10. A system for supplying a current pulse to a core memory, said system having a minimal current buildup time interval and a minimal power drain comprising:

a transformer having a selectively variable primary/secondary turns ratio;

means for connecting the secondary of said transformer to said core memory; means for initially energizing the primary of said transformer through a current path having a minimal L/R time constant so that a current of predetermined value is driven through said secondary winding within a very short time interval;

means for subsequently reducing the current flow through said primary for reducing the power drain; and

means for changing said primary/secondary turns ratio for maintaining a desired magnitude of current flow through said secondary winding during the period that the current flow is reduced through said primary.

11. A system drawing minimal power for supplying a current pulse of predetermined magnitude and minimal buildup time interval to the high inductance inhibit windings of a bit plane of a coincident current memory,

comprising:

a transformer having first and second series connected primary windings and a secondary winding, said secondary winding providing a balanced output drive wherein neither end of the winding is grounded;

means for connecting one 'end of said secondary winding to a pair of inhibit windings of said bit plane, one of said windings being respectively threaded through a plurality of memory cores of said bit plane and the other of said windings being respectively threaded through the remaining memory cores of said bit plane;

means including a pair of diodes respectively connected to said first and second inhibit sense windings to provide a return current path to the other side of said secondary winding;

a power supply supplying a voltage of predetermined magnitude;

a first transistor switch connected in series with said power supply and said first primary winding to provide a first current path when said first transistor switch is on;

a second transistor switch, diode and resistor connected in series with the said first and second primary windings to provide a second current path when said second transistor switch is on and said firsttransistor switch is off;

time control means coupled to said first and second transistor switches for i. turning said first transistor switch on for a sufficient time interval to drive a current of predetermined value through said secondary winding to said core stack, and

. turning off said first transistor switch and turning on said second transistor switch to decrease the current drawn from said power supply and thereby draw less power from said power supply while increasing the primary/secondary turns ratio and thereby maintaining the desired magnitude of current flow through said secondary. 12. The system described in claim 1 1 including a sense amplifier for distinguishing between ONE and ZERO signals in the voltage outputs of the bit plane having a first input connected to one end of one of said inhibit windings and another input connected to one end of the other of said inhibit windings.

13. The method for generating a current pulse of predetermined magnitude for driving a high inductance winding of a memory core stack comprising the steps of:

energizing the primary winding of a transformer through a current path of minimum resistance so that a current of predetermined value flows through the transformer secondary winding and the winding of the core stack connected thereto within a very short time interval; and

subsequently reducing the magnitude of current that a current of predetermined value flows through the transformer secondary winding and the winding of the core stack connected thereto within a very short time interval;

subsequently reducing the magnitude of current through the primary winding; and

increasing the number of turns of said primary winding through-which said reduced magnitude of current flows so that said reduced magnitude of current in the primary does not cause a proportionate reduction in magnitude of the current pulse driving said core stack. 

1. A system for supplying a predetermined magnitude of current to a core memory, said system having a minimal current buildup time interval and a minimal power drain, comprising: a transformer having first and second series connected primary windings and a secondary winding; means for connecting said secondary winding to said core memory; a voltage source; a first switch connected in series with said voltage source and said first primary winding to provide a first current path; a second switch connected in series with said voltage source and said first and second primary windings to provide a second current path; and means coupled to said first and second switches for i. closing said first switch for a sufficient interval to drive a current of predetermined value through said secondary winding to said core memory, and ii. opening said first switch after said second switch has been closed; means coupled to said second current path to limit the current flow therethrough and thereby limit the power drain from said voltage source, the increase in primary/secondary turns ratio maintaining a desired magnitude of current flow through said secondary while decreasing the power drain from said voltage source.
 2. The system described in claim 1 wherein said means coupled to said second current path to limit the current flow therethrough comprises a resistor.
 3. The system described in claim 1 including means connected in said second current path for preventing the flow of current therethrough when said first switch is closed so that the closing of said second switch does not result in current flow through said second current path until after said first switch has been opened.
 4. The system described in claim 3 wherein said means connected in said second current path is a diode.
 5. The system described in claim 1 including a capacitor coupled to said primary windings, said capacitor being charged when the second switch is opened and the current flowing through the inductance of said core memory causes a voltage to be induced in the secondary winding which in turn induces a voltage in the primary winding.
 6. The system described in claim 5 including a resistor connected in series with said capacitor so that the voltage across said primary winding is critically damped when the second switch is opened.
 7. The system described in claim 1 wherein said first and second switches are transistors.
 8. The system described in claim 1 wherein said secondary winding provides a balanced drive for the core memory wherein neither end of the secondary winding is grounded.
 9. A system for supplying a current pulse to a core memory, said system having a minimal current buildup time interval and a minimal power drain comprising: a transformer having a selectively variable primary/secondary turns ratio; means for connecting the secondary of said transformer to said core memory; means for initially energizing the primary of said transformer through a current path having a minimal L/R time constant so that a current of predetermined value is driven through said secondary winding within a very short time interval; and means for changing said primary/secondary turns ratio while simultaneously reducing the current flow through said primary so that the power drain is reduced while a desired magnitude of current flow is maintained through said secondary winding.
 10. A system for supplying a current pulse to a core memory, said system having a minimal current buildup time interval and a minimal power drain comprising: a transformer having a selectively variable primary/secondary turns ratio; means for connecting the secondary of said transformer to said core memory; means for initially energizing the primary of said transformer through a current path having a minimal L/R time constant so that a current of predetermined value is driven through said secondary winding within a very short time interval; means for subsequently reducing the current flow through said primary for reducing the power drain; and means for changing said primary/secondary turns ratio for maintaining a desired magnitude of current flow through said secondary winding during the period that the current flow is reduced through said primary.
 11. A system drawing minimal power for supplying a current pulse of predetermined magnitude and minimal buildup time interval to the high inductance inhibit windings of a bit plane of a coincident current memory, comprising: a transformer having first and second series connected primary windings and a secondary winding, said secondary winding providing a balanced output drive wherein neither end of the winding is grounded; means for connecting one end of said secondary winding to a pair of inhibit windings of said bit plane, one of said windings being respectively threaded through a plurality of memory cores of said bit plane and the other of said windings being respectively threaded through the remaining memory cores of said bit plane; means including a pair of diodes respectively connected to said first and second inhibit sense windings to provide a return current path to the other side of said secondary winding; a power supply supplying a voltage of predetermined magnitude; a first transistor switch connected in series with said power supply and said first primary winding to provide a first current path when said first transistor switch is on; a second transistor switch, diode and resistor connected in series with the said first and second primary windings to provide a second current path when said second transistor switch is on and said first transistor switch is off; time control means coupled to said first and second transistor switches for i. turning said first transistor switch on for a sufficient time interval to drive a current of predetermined value through said secondary winding to said core stack, and ii. turning off said first transistor switch and turning on said second transistor switch to decrease the current drawn from said power supply and thereby draw less power from said power supply while increasing the primary/secondary turns ratio and thereby maintaining the desired magnitude of current flow through said secondary.
 12. The system described in claim 11 including a sense amplifier for distinguishing between ONE and ZERO signals in the voltage outputs of the bit plane having a first input connected to one end of one of said inhibit windings and another input connected to one end of the other of said inhibit windings.
 13. The method for generating a current pulse of predetermined magnitude for driving a high inductance winding of a memory core stack comprising the steps of: energizing the primary winding of a transformer through a current path of minimum resistance so that a current of predetermined value flows through the transformer secondary winding and the winding of the core stack connected thereto within a very short time interval; and subsequently reducing the magnitude of current flowing through the primary winding of said transformer while modifying the primary/secondary turns ratio of said transformer so that the power drain is reduced while maintaining a desired magnitude of current flow through said secondary winding.
 14. The method for generating a current pulse of predetermined magnitude for driving a high inductance winding of a memory core stack comprising the steps of: energizing the primary winding of a transformer through a current path of minimum resistance so that a current of predetermined value flows through the transformer secondary winding and the winding of the core stack connected thereto within a very short time interval; subsequently reducing the magnitude of current through the primary winding; and increasing the number of turns of said primary winding through which said reduced magnitude of current flows so that said reduced magnitude of current in the primary does not cause a proportionate reduction in magnitude of the current pulse driving said core stack. 